The present invention relates, in general, to electronics, and more particularly, to semiconductors, structures thereof, and methods of forming semiconductor devices.
In the past, the semiconductor industry utilized various methods and circuits to form current sense signals that were representative of a current through a transistor such as a power metal oxide semiconductor (MOS) field effect transistor (FET). One particular circuit configuration utilized two transistors with commonly connected drains and gates and separate sources. The active area of the sources was ratioed to each other so that the current flowing through one transistor was a small percentage of the current flowing through the other transistor. This was often called a mirror transistor configuration or a SenseFET. It was found that the value of the current through the small transistor was not always a constant ratio to the value of the current through the larger transistor. Therefore, some configurations included a separate Kelvin connection that facilitated connecting a Kelvin sense terminal directly to the source of the large transistor.
FIG. 1 illustrates a prior art example of a SenseFET 215 that had a main transistor (MT) and a sense transistor (S). The source(SS) of the sense transistor (ST) was brought to a connection external to the package of SenseFET 215. The source (MS) of the main transistor (MT) was brought to a connection external to the package of SenseFET 215 and the Kelvin sense (KS) was brought to another external terminal of the package. In some configurations, an amplifier 220 was connected in a virtual ground or virtual earth connection. It was believed that such a configuration provided a signal at the sense source (SS) that was a more accurate representation of the current through the main transistor by maintaining the sense source (SS) and the main source (MS) at the same potential. However, it has been found that even this configuration resulted in inaccuracies between the value of the current through the main and sense transistors.
Accordingly, it is desirable to have a current sense circuit and method that provides a signal that more accurately represent the value of the current through the main transistor and the current through the drain of the combined main and sense transistor.
For simplicity and clarity of the illustration, elements in the figures are not necessarily to scale, and the same reference numbers in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein current carrying electrode means an element of a device that carries current through the device such as a source or a drain of an MOS transistor or an emitter or a collector of a bipolar transistor or a cathode or anode of a diode, and a control electrode means an element of the device that controls current through the device such as a gate of an MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain N-channel or P-Channel devices, or certain N-type or P-type doped regions, a person of ordinary skill in the art will appreciate that complementary devices are also possible in accordance with the present invention. It will be appreciated by those skilled in the art that the words during, while, and when as used herein relating to circuit operation are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay, such as a propagation delay, between the reaction that is initiated by the initial action. The use of the word approximately or substantially means that a value of an element has a parameter that is expected to be very close to a stated value or position. However, as is well known in the art there are always minor variances that prevent the values or positions from being exactly as stated. It is well established in the art that variances of up to at least ten per cent (10%) (and up to twenty per cent (20%) for semiconductor doping concentrations) are reasonable variances from the ideal goal of exactly as described. For clarity of the drawings, doped regions of device structures are illustrated as having generally straight line edges and precise angular corners. However, those skilled in the art understand that due to the diffusion and activation of dopants the edges of doped regions generally may not be straight lines and the corners may not be precise angles.
In addition, the description illustrates a cellular design (where the body regions are a plurality of cellular regions) instead of a single body design (where the body region is comprised of a single region formed in an elongated pattern, typically in a serpentine pattern). However, it is intended that the description is applicable to both a cellular implementation and a single base implementation.